The present disclosure relates to an output circuit to be used for a semiconductor integrated circuit device.
In a semiconductor integrated circuit device, an interface circuit for inputting and outputting a signal from and to an external device is required to operate at a high speed with low power consumption. In order to achieve high speed operation as well as low power consumption, a transistor to be used as an I/O transistor operates on a low voltage of, for example, 1.8 V. Meanwhile, the interface circuit needs to be operable to input and output a high voltage signal of, for example, 3.3 V.
Japanese Unexamined Patent Publication No. 2007-60201 discloses a technique to implement an output circuit outputting a high voltage signal outside, using a transistor operating on a low voltage. In this technique, the low-voltage transistor is connected in a cascade between a high-voltage power source and an output pad to relieve a source-drain voltage of the low-voltage transistor. A p-type transistor driving an output signal has (i) a source connected to the high-voltage power source, (ii) a drain connected to the output pad via another transistor, and (iii) a gate provided with a signal transiting between a high voltage and a low voltage.
However, the technique disclosed in Japanese Unexamined Patent Publication No. 2007-60201 could cause an increase in delay of the output signal when an externally supplied power source voltage varies. Specifically, a gate-source voltage, which switches the p-type transistor driving the output signal into a conductive state, is equivalent to the difference between a voltage of the high-voltage power source and a voltage of a low-voltage power source. However, this gate-source voltage significantly decreases when the voltage of the high-voltage power source drops and the voltage of the low-voltage power source rises. The drop in the gate-source voltage when the p-type transistor goes to the conductive state leads to a decrease in driving capability of the p-type transistor, eventually causing an increase in delay of the output signal. Meanwhile, the p-type transistor could be increased in size to complement the driving capability of the transistor to reduce the delay of the output signal; however, this is not preferable since the increase in size leads to an increase in circuit area.
The present disclosure intends to provide an output circuit capable of high speed operation without causing an increase in a circuit area.